FPGA Oriented Intra Angular Prediction Image Generation Hardware for HEVC Video Coding

This work proposes a novel architecture for intra prediction image generation of High Efficiency Video Coding (HEVC) standards oriented to FPGA. HEVC intra prediction is highly-extended from H.264 in those of mode and block size to realize the high flexibility. From the point of view of hardware, however, this flexibility cause an increasing required the number of MUXs although MUXs tend to be a bottleneck of area and frequency in the case of FPGA. In this paper we propose a Reshaping Buffered Architecture which enables reduction the number of MUXs, drastically. Experimental results show that our proposed architecture can reduce up to 70% of number of MUXs compared with conventional raster scan based architecture. This resulted in a marked improvement of maximum frequency by 43% and LUT usage by 51%, respectively.